Programmable logic devices (“PLDs”) are well known in the art. They provide reprogrammable logic in the form of lookup tables, interconnect, and the like. Their flexibility allows a single architecture to be used for many different functions, which can yield lower system cost and faster development time than other solutions, such as application-specific integrated circuits (“ASICs”). Illustrative PLDs are described in detail in Cliff et al. U.S. Pat. No. 5,689,195 and Jefferson et al. U.S. Pat. No. 6,215,326, which are hereby incorporated by reference in their entirety. As used herein, a PLD refers to any integrated circuit (“IC”) with programmable logic. Thus, a hybrid IC with both programmable and hard-wired logic, such as a structured ASIC, is still referred to herein as a PLD.
One potential disadvantage of using PLDs is reduced performance in certain scenarios. For instance, a soft (reprogrammable) processor on the PLD may not be able to perform some real-time control operations, such as monitoring the PLD's status and reporting that status to an appropriate master device. Such difficulties are often overcome by using a separate external processor which is mounted on the same board as the PLD. The PLD may communicate with that processor using a high-speed transfer mechanism, such as a gigabit media access controller (“MAC”).
Similarly, real-time remote configuration of the PLD often requires the use of an external processor, a high-speed transfer mechanism, and a direct memory access (“DMA”) engine. Although solutions involving dedicated external circuitry are generally effective, their cost can often be quite high.
In view of the foregoing, it would be desirable to provide circuitry and methods enabling real-time control and configuration of a PLD while reducing system cost.